Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures

Tosun S.

JOURNAL OF SUPERCOMPUTING, vol.62, no.1, pp.265-289, 2012 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 62 Issue: 1
  • Publication Date: 2012
  • Doi Number: 10.1007/s11227-011-0720-3
  • Page Numbers: pp.265-289


Scheduling periodic tasks onto a multiprocessor architecture under several constraints such as performance, cost, energy, and reliability is a major challenge in embedded systems. In this paper, we present an Integer Linear Programming (ILP) based framework that maps a given task set onto an Heterogeneous Multiprocessor System-on-Chip (HMPSoC) architecture. Our framework can be used with several objective functions; minimizing energy consumption, minimizing cost (i.e., the number of heterogeneous processors), and maximizing reliability of the system under performance constraints. We use Dynamic Voltage Scaling (DVS) for reducing energy consumption while we employ task duplication to maximize reliability. We illustrate the effectiveness of our approach through several experiments, each with a different number of tasks to be scheduled. We also propose two heuristics based on Earliest Deadline First (EDF) algorithm for minimizing energy under performance and cost constraints. Our experiments on generated task sets show that ILP-based method reduces the energy consumption up to 62% percent against a method that does not apply DVS. Heuristic methods obtain promising results when compared to optimal results generated by our ILP-based method.