Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs

Gokalan A., TOSUN S., DAL D.

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, vol.36, no.6, pp.743-756, 2020 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 36 Issue: 6
  • Publication Date: 2020
  • Doi Number: 10.1007/s10836-020-05913-1
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Academic Search Premier, Aerospace Database, Communication Abstracts, Compendex, INSPEC, Metadex, DIALNET, Civil Engineering Abstracts
  • Page Numbers: pp.743-756
  • Keywords: Soft error, FPGA, Reliability, Arithmetic circuits
  • Hacettepe University Affiliated: Yes


Designing an application in hardware under inversely competing constraints such as area and performance with different objective functions such as power consumption and reliability of the circuits is a cumbersome task. Having different versions of the same resource type during the design process may ease this burden since there can be several alternative resources to meet the given constraints. In this paper, we characterize a library of some commonly used arithmetic circuits in FPGAs in terms of the speed, area, power consumption, and vulnerability to error propagation as the reliability parameter. Specifically, we implemented four well-known adders and two multipliers in an SRAM-based FPGA that is a part of Xilinx's Zynq-7000 SoC platform. We then injected errors to the configuration bits of the circuits to evaluate the error propagation. The results show that different versions of the same resources can have different reliability values in addition to the area, latency, and power values.