FIT: Fast Irregular Topology generation algorithm for application specific NoCs


Tosun S.

IEICE ELECTRONICS EXPRESS, cilt.7, ss.1132-1138, 2010 (SCI İndekslerine Giren Dergi) identifier identifier

  • Cilt numarası: 7 Konu: 15
  • Basım Tarihi: 2010
  • Doi Numarası: 10.1587/elex.7.1132
  • Dergi Adı: IEICE ELECTRONICS EXPRESS
  • Sayfa Sayıları: ss.1132-1138

Özet

This work presents a low complexity irregular topology generation algorithm for Netwok-on-Chip (NoC) design flow. The objective of the algorithm is minimizing the energy consumption of the final design. We tested the effectiveness of our algorithm by comparing it with its earlier counterparts on several multimedia applications.