FICS: A machine learning-based feasibility inference classifier for accelerating simulated annealing in energy- and reliability-aware high-level synthesis
INTEGRATION, THE VLSI JOURNAL, cilt.102901, ss.1-33, 2026 (SCI-Expanded, Scopus)
- Yayın Türü: Makale / Tam Makale
- Cilt numarası: 102901
- Basım Tarihi: 2026
- Doi Numarası: 10.1016/j.vlsi.2026.102901
- Dergi Adı: INTEGRATION, THE VLSI JOURNAL
- Derginin Tarandığı İndeksler: Applied Science & Technology Source, Academic Search Ultimate (EBSCO), Engineering Source (EBSCO), Scopus, Science Citation Index Expanded (SCI-EXPANDED), Compendex, INSPEC, zbMATH
- Sayfa Sayıları: ss.1-33
- Hacettepe Üniversitesi Adresli: Evet
Özet
High-Level Synthesis (HLS) design space exploration jointly optimizing energy and reliability under latency and area constraints across voltage island configurations is a combinatorial NP-hard problem. In Simulated Annealing (SA)-based HLS, feasibility evaluation through list scheduling dominates runtime. This paper proposes the Feasibility Inference Classifier for Scheduling (FICS), a LightGBM-based classifier embedded in the Simulated Annealing (SA) inner loop to reject likely infeasible candidate allocations before scheduling. FICS is trained on 46 schedule-context features extracted from SA exploration trajectories and deployed as a header-only C++ evaluator compiled directly into the optimization binary. Experiments on eight HLS benchmarks and three optimization modes show wall-clock speedups of up to 4.63×, with a mean of 1.41× across all instances; although relaxed instances can fall below 1×. Direct instrumentation confirms that FICS reduces scheduler invocations by 22.6%–61.2%. The acceleration is not quality-neutral: across 55 benchmark/constraint instances per mode, FICS-SA increases energy by 3.06% on average and the balanced objective by 3.50%, while reliability shows a small borderline decrease of 0.47% (p=0.0505; 44/55 ties). The degradation is strongly heterogeneous and concentrated in tightly area-constrained cases, which also produce the largest speedups. Component profiling shows that FICS gating is beneficial when the avoided scheduling cost exceeds classifier overhead, yielding an explicit runtime-quality trade-off rather than cost-free acceleration.