A Resource-Efficient Hardware Accelerator for LightGlue on Reconfigurable Embedded Devices
8th International Congress on Human-Computer Interaction, Optimization and Robotic Applications, ICHORA 2026, Ankara, Türkiye, 21 - 23 Mayıs 2026, (Tam Metin Bildiri)
- Yayın Türü: Bildiri / Tam Metin Bildiri
- Doi Numarası: 10.1109/ichora69329.2026.11537192
- Basıldığı Şehir: Ankara
- Basıldığı Ülke: Türkiye
- Anahtar Kelimeler: FPGA, hardware-software co-design, LightGlue Acceleration, transformers
- Hacettepe Üniversitesi Adresli: Evet
Özet
Feature matching is a fundamental step in computer vision tasks such as simultaneous localization and mapping (SLAM). While transformer-based matchers like LightGlue offer state-of-the-art accuracy, their high computational complexity and memory footprint hinder deployment on resourceconstrained edge devices. This paper proposes a hardwareaccelerated, resource-efficient implementation of the LightGlue inference pipeline on an FPGA-based MPSoC. To overcome embedded resource limitations, we introduce a layer-folded architecture that time-multiplexes hardware resources for LightGlue's multi-layer processing, significantly reducing logic utilization. We propose a from-scratch training methodology with deep supervision that enables the network to natively learn ReLUcompatible attention patterns, eliminating the accuracy collapse observed in naive activation substitution. Through systematic ablation experiments, we demonstrate that ReLU attention incurs only 5.5% accuracy loss while providing over 85% resource savings, and empirically show that normalization-free alternatives (Dynamic Tanh) are unsuitable for matching tasks due to the absence of per-token normalization. Our design achieves realtime performance of up to 200 FPS on the Xilinx ZCU102, delivering a 7.1x speedup and up to 44x energy efficiency improvement over the NVIDIA Jetson AGX Orin, while matching the throughput of a RTX A2000 desktop-class GPU at a fraction of the power budget.