© 2022 Elsevier LtdContinuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit's reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits.