FIT: Fast Irregular Topology generation algorithm for application specific NoCs

Creative Commons License

Tosun S.

IEICE ELECTRONICS EXPRESS, cilt.7, sa.15, ss.1132-1138, 2010 (SCI-Expanded) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 7 Sayı: 15
  • Basım Tarihi: 2010
  • Doi Numarası: 10.1587/elex.7.1132
  • Dergi Adı: IEICE ELECTRONICS EXPRESS
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Sayfa Sayıları: ss.1132-1138
  • Hacettepe Üniversitesi Adresli: Evet

Özet

This work presents a low complexity irregular topology generation algorithm for Netwok-on-Chip (NoC) design flow. The objective of the algorithm is minimizing the energy consumption of the final design. We tested the effectiveness of our algorithm by comparing it with its earlier counterparts on several multimedia applications.