Derin Sinir Ağları Hızlandırıcıları için Topolojiye Duyarlı Budama ve Eşleme Algoritmalarının Geliştirilmesi
TÜBİTAK Projesi, 1001 - Bilimsel ve Teknolojik Araştırma Projelerini Destekleme Programı, 2023 - 2026
- Proje Türü: TÜBİTAK Projesi
- Destek Programı: 1001 - Bilimsel ve Teknolojik Araştırma Projelerini Destekleme Programı
- Başlama Tarihi: Kasım 2023
- Bitiş Tarihi: Mayıs 2026
Proje Özeti
Novelty: Deep Neural Networks (DNN) have gained wide adoption in various domains in recent years; however, their high computational requirements have made it challenging to implement them in resource-constrained Internet of Things (IoT) devices. DNNs often require multi-processor environments or high-capacity GPU systems, leading to performance loss and high energy consumption, especially when dealing with large data volumes and data transmission between DNN layers. To overcome these limitations, it is crucial to reduce the size of DNN structures without compromising their effectiveness and run them on application-specific architectures optimized for data communication. One promising approach for reducing the size of DNN models is to prune unnecessary model elements, such as weights, neurons, and filters, while maintaining performance. However, DNN models pruned with non-structural methods may be inadequate or even detrimental in architectures designed for standard structures such as CPUs and GPUs. Therefore, it is more efficient to run pruned models in architectures that offer regular and flexible communication, such as Network-on-Chip (NoC). However, existing pruning methods for DNNs are not optimized for NoC architectures, and there is a need for optimization algorithms that consider the NoC structure and map the pruned system in an energy-efficient manner. In this project, we aim to develop NoC topology-aware heuristic and metaheuristic methods that can perform weight and neuron pruning, optimally group neurons in the pruned DNN structure, and map them to the NoC architecture in an energy-efficient manner.
Method: To accomplish our objectives, we will conduct a study that evaluates the compatibility and adaptability of various pruning methods to the NoC architecture. Specifically, we will test different structural and non-structural pruning methods on different benchmarks using two distinct GPU architectures. Subsequently, we will develop heuristic pruning methods that are aware of the NoC topology and neuron grouping algorithms that minimize the total data flow between groups. To minimize energy consumption, we will then create mapping algorithms that minimize the amount of data communication required for grouped neurons. Since heuristic algorithms may get stuck at local minima, we will develop metaheuristic algorithms, such as simulated annealing or genetic algorithms, to overcome this issue. Furthermore, we aim to develop both heuristic and metaheuristic pruning and mapping algorithms for the concentrated mesh (Cmesh) topology type, which is more suitable for some DNN structures.
Management and widespread impact: The project team has prior experience with TÜBİTAK projects that involve developing optimization algorithms for application mapping to NoC architectures, as well as expertise in the field of artificial intelligence. Based on the knowledge and methods gained from previous projects that can be adapted to the current project, we are confident that this team will successfully complete the presented project. We aim to publish at least four articles in respected journals and four conference publications. Additionally, we will support a Ph.D. student, two master's students, and an undergraduate student with the aim of training and fostering new researchers in the field.