KİM, Y. Et Al. 2005. Formal verification of pipelined synthesized designs by exploiting intermediary RTLs. International Journal of Modelling and Simulation , vol.25, no.3 , 210-220.

KİM, Y., Tosun, S., KOÇ, H., KOPURİ, S., & MANSOURİ, N., (2005). Formal verification of pipelined synthesized designs by exploiting intermediary RTLs. International Journal of Modelling and Simulation , vol.25, no.3, 210-220.

KİM, YOUNGSİK Et Al. "Formal verification of pipelined synthesized designs by exploiting intermediary RTLs," International Journal of Modelling and Simulation , vol.25, no.3, 210-220, 2005

KİM, YOUNGSİK Et Al. "Formal verification of pipelined synthesized designs by exploiting intermediary RTLs." International Journal of Modelling and Simulation , vol.25, no.3, pp.210-220, 2005

KİM, Y. Et Al. (2005) . "Formal verification of pipelined synthesized designs by exploiting intermediary RTLs." International Journal of Modelling and Simulation , vol.25, no.3, pp.210-220.

@article{article, author={YOUNGSİK KİM Et Al. }, title={Formal verification of pipelined synthesized designs by exploiting intermediary RTLs}, journal={International Journal of Modelling and Simulation}, year=2005, pages={210-220} }